In order to enable a higher component density on integrated circuits, much effort is invested in decreasing the size of these components.
Currently, industry is striving to reach the 10 nm technology node. In this node, the gate length in transistors may be smaller than 20 nm. Components currently envisioned for this technology node such as Si FinFET and high mobility channel devices need to fulfil stringent requirements concerning their external resistance.
According to the ITRS roadmap edition 2012, the external resistance of these devices will need to be reduced to less than 100 Ωμm for Ge/III-V and less than 180 Ωμm for Si.
A large part of the resistance is coming from the contact resistance (contact plug or local interconnect to the source and drain areas).
Typically contact resistivity values down to 10−9 to 10−8 Ωμm2 will be required to fulfil the requirements for high performance.
With the use of SiGe as source or drain material (with a NiSi or Ni(Si)Ge top layer, or even with direct contacting) one is able to achieve much lower contact resistances for both Si pMOS and Ge pMOS than for nMOS devices. For instance, in Ge pMOS, fermi-level pinning around 0.6 eV leads to good ohmic contacts on Ge pMOS, but leads to Schottky barrier contacts on Ge nMOS.
The lowest specific contact resistivities for Ge nMOS have been achieved with MIS (Metal-Insulator-Semiconductor) contacts but even then only 10−7 Ω·μm2 has been achieved. Next to that, high doping levels of the source and drain areas are difficult to achieve in Ge due to problems with activation of n-type dopants.
In the case of Si nMOS, contact resistivities below 10−8 Ωμm2 can so far only be achieved when the doping of the source and drain areas is above 1020 cm−3 which is quite challenging in narrow fins devices. Especially nMOS devices, where As (for Si) and P (for Ge) are typical implant species, suffer from amorphization and problematic recrystallization which leads to high junction resistance. Plasma doping to increase conformality and hot implant to reduce amorphization have been put forward as possible solutions. However, all these techniques require a rather complex integration scheme.
US2012/0168877 proposes a device having an electrical contact where the conductive contact material is separated from the source or drain region by a III-V material. Such an arrangement allegedly produces improved current flow in the Si or Ge nMOS. The present inventors have however observed that the resistivity of such an arrangement is disappointingly high. There remains therefore a need in the art for new good MOS arrangements, and especially nMOS arrangements, permitting low contact resistivities.